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The labs are building their own chips. Inference is why

OpenAI’s Jalapeño ASIC taped out in nine months; DeepSeek is reportedly designing its own inference part. Why the serving layer, where AI’s economics live, is pulling every lab into custom silicon.

Two announcements a week apart tell one story. OpenAI and Broadcom unveiled Jalapeño, OpenAI’s first custom inference processor, a reticle-sized ASIC taped out in a nine-month cycle and targeting deployment from late 2026, per Tom’s Hardware’s analysis. Days later, Reuters reported that DeepSeek is developing its own inference chip. The labs are done renting the layer where their economics live.

Why everyone suddenly wants inference silicon

Training happens once; inference happens every time a user asks. As we argued in our margins analysis, serving cost is the gravity of the whole AI economy, it decides whether products at the application layer keep 25 percent or 70 percent of their revenue. A chip tuned to one lab’s serving patterns attacks that cost directly: OpenAI says engineering samples already run production workloads at target frequency and power.

The strategic logic mirrors what Google did with TPUs a decade ago, but the timeline is new: nine months from design start to tape-out, with OpenAI using its own models to accelerate chip design. Silicon iteration is starting to move at software speed, which also reshapes demand on the memory supply chain that feeds every accelerator.

The two races inside the race

The American version is about margin and Nvidia leverage: every hyperscaler and lab wants a second source it controls. The Chinese version, DeepSeek’s, is about sovereignty under export controls, where dependence on any foreign supplier is an existential risk. Same instinct, different stakes: control the layer your economics depend on.

The economics of owning the silicon

The margin math explains the urgency. A lab renting accelerators pays for generality it does not need: a merchant GPU must run every workload well, while a lab’s inference traffic is one workload repeated billions of times, with known model architectures, known batch sizes and known precision requirements. An ASIC that sheds the unused generality can serve the same tokens for a fraction of the power and cost per query, and at the scale frontier labs now operate, single-digit percentage gains in serving efficiency compound into billions of dollars a year.

The risk is that custom silicon is a bet against your own roadmap. A chip frozen at tape-out serves the architectures its designers expected; a research breakthrough that changes attention mechanisms or precision needs can strand the investment before deployment. That is why the nine-month design cycle matters as much as the chip itself: shorter iteration loops shrink the window in which a design can go stale, and using models to design the silicon that serves models is the flywheel that keeps shortening it. Nvidia’s real moat was never only the hardware, it was that nobody could afford to be wrong about silicon for three years. At nine-month cycles, being wrong gets survivable, and the calculus that kept everyone renting starts to break.

What to watch

Watch whether Jalapeño’s late-2026 deployment holds, which foundry DeepSeek can actually use, and Nvidia’s pricing response, the clearest tell of how seriously it takes the custom-silicon exodus. The same sovereignty logic is now visible one layer up the stack in China’s open-weight model strategy.

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Dr. Joseph Joshua

Dr. Joseph Joshua is the founder and editor of Corewire. A medical doctor by training, he brings the evidence-first discipline of clinical medicine to technology journalism: claims get checked against primary sources before they get published. He has produced technology and B2B content for companies across…

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